1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to an internal clock generation circuit suitable for use in a synchronous semiconductor memory device activated in synchronism with a system clock.
2. Description of the Related Art
A semiconductor memory device operated in synchronism with a system clock supplied thereto has recently been required to speed up its operating speed with an increase in the frequency of the system clock. Therefore, a transfer delay time between the input of the system clock to the semiconductor memory device and the output of data therefrom becomes large relative to a clock cycle of the system clock. Thus, this leads to a malfunction.
FIG. 13(a) shows a data output-timing chart of a semiconductor memory device activated in synchronism with a system clock. The drawing shows the manner in which the system clock (hereinafter called "external clock .PHI.ext") inputted to the semiconductor memory device is transferred within the semiconductor memory device with a delay time td0 and defined as a data output timing clock CLKd, and data .PHI.out is outputted in synchronism with the clock. The data .PHI.out is outputted with a delay dout of an output circuit with respect to the clock CLKd. The data is transmitted and received according to a strobe signal .PHI.s.
When, however, the operating frequency of the external clock .phi.ext becomes high, the strobe signal .phi.s is outputted before the output of .phi.out is fixed, so that a malfunction occurs.
In order to solve such a problem, an internal clock generation circuit such as Phase Locked Loop (PLL), Delay Locked Loop (DLL) employed in a semiconductor memory device has been proposed to implement chip's internal operations synchronized with a system clock.
FIG. 14 is a schematic diagram of a conventional internal clock generation circuit. The internal clock generation circuit comprises a delay line 102 for generating such amount of a delay thereof as to minimize the phase difference between an external clock .PHI.ext and a data output .PHI.out, a control circuit 200 for controlling the delay line 102, and a monitor circuit 106 for monitoring a delay amount of an output circuit 104 of a semiconductor memory device.
The control circuit 200 comprises a phase comparator 100 and a shift register 101. The phase comparator 100 compares the phase of the external clock next and that of a clock .phi.fd, which is obtained by delaying an internal clock .phi.int by a delay time dout of the output circuit 104 via the monitor circuit 106 and fed back from the monitor circuit 106 to thereby detect the phase difference therebetween and outputs a detected signal .phi.1 to the shift register 101. The shift register 101 counts the detected signal .phi.1 and outputs a control signal .phi.2 to the delay line 102 in response to the detected signal .phi.1 to control the delay line 102.
The delay line 102 is controlled according to the control signal .phi.2 and controls or adjusts such a delay amount as to minimize the phase difference between the external clock .phi.ext and the data output .phi.out.
FIG. 16 is a data output timing chart of the circuit shown in FIG. 14. When the external clock .phi.ext is inputted to the delay line 102, the amount of a delay of the delay line 102 is controlled by the control signal .phi.2 so that such an internal clock .phi.int that the delay amount tLine becomes tLine =tCK-dout (where tCK: cycle time of clock), is generated. It is therefore feasible to provide a data output .phi.out minimized in delay with respect to the external clock .phi.ext. Thus, the internal clock generation circuit generates such an internal clock .phi.int as to achieve data output .phi.out delayed by one cycle from the external clock .phi.Oext.
FIG. 15 is a diagram showing a circuit configuration of the delay line 102 lying within the conventional internal clock generation circuit. As shown in FIG. 15, the delay line 102 comprises delay elements 202 and selects any of TAPs (TAP1 through TAPn) thereof in response to a control signal .phi.2 to control the number of effective delay elements, thereby controlling or adjusting the amount of a delay of the external clock .phi.ext. Incidentally, a unit delay time of each delay element 202 will be defined as a delay step.
However, the conventional internal clock generation circuit is accompanied by a problem in that since an internal clock generable frequency range is determined based on (delay step).times.(number of delay elements), the number of the delay elements must be increased to generate the internal clock in a wide frequency range when the delay step is reduced, thus leading to an increase in chip area. When the operating frequency is 66 MHz, for example, the cycle time of a clock results in 15 ns. The number of the delay elements at the time that the delay step is 0.30 ns, needs 15.div.0.30=50. Assuming that the delay step is set to 0.15 ns equivalent to one-half the delay step of 0.30 ns at this time, the number of the delay elements needs 100 equivalent to twice the number of the delay elements 50.